A Foreground Mismatch and Memory Harmonic Distortion Calibration Algorithm for TIADC

This paper proposes a foreground digital calibration algorithm that estimates and corrects the offset, gain, time-skew mismatches for time-interleaved analog-to-digital converters (TIADCs) furthermore our is designed to correct harmonic distortion introduced by presence of nonlinear front-end. We propose novel simplified non-linear model in place more complex conventional Volterra series based structure. The mismatch estimation technique on Fast Fourier Transform (FFT) proposed estimate various time-interleaving simultaneously. A Taylor-based applied compensate these mismatches. also consider choice an appropriate time reference correction theoretical analysis. estimating inverting assumed $3^{\text {rd}}$ order nonlinearity with fractional delay. To do this, we design customized filter offline process. Our algorithms are operate any Nyquist zone. techniques verified Xilinx Zynq UltraScale+ RFSoC ZCU111 evaluation kit containing 12-bit, 4.096 GHz TI-ADC 8 sub-ADCs operating notation="LaTeX">$2^{\text {nd}}$ Accordingly, observed improvement SFDR 14 dB alone up another 12 enabled.